INTERLAYER DIELECTRIC FOR NON-PLANAR TRANSISTORS

摘要

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

主权项

1. An integrated circuit (IC) structure, comprising:
a fin having a source and a drain, wherein the fin comprises silicon; a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode; a capping structure over the gate electrode, wherein the capping structure comprises silicon and nitrogen; a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen, and wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer; and a contact extending through the dielectric layer to one of the source and the drain.