STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES

摘要

Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.

主权项

1. A method comprising:
fabricating an NMOS transistor device comprising a substrate and a gate structure disposed over the substrate, the substrate comprising a channel region underlying, at least partially, the gate structure, the fabricating comprising: forming a stress region by performing an ion implantation process consisting of implanting nitrogen ions into the substrate to form the stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region.