CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

摘要

A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

主权项

1. A method of manufacturing a chip-stacked semiconductor package, the method comprising:
preparing a base wafer, the base wafer including a plurality of first chips, each of the plurality of first chips having a first front surface, a first back surface that is opposite to the first front surface, and a first connection member on the first front surface; preparing a plurality of second chips, each of the plurality of second chips having a second front surface, a second back surface that is opposite to the second front surface, and a second connection member on the second front surface; stacking the plurality of second chips on the plurality of first chips such that the second connection member is electrically connected to the first connection member between the first front surface and the second front surface; sealing the plurality of second chips by using a first sealing member; forming a first through-silicon via (TSV) that is electrically connected to the second connection member in each of the plurality of second chips; separating the plurality of first chips and the plurality of second chips, the plurality of first chips and the plurality of second chips being on the base wafer, each first connection member and a corresponding second connection member being symmetric with respect to each other.