| 摘要 |
PURPOSE:To reduce power consumption by reducing the gate voltages of transistors T8, T5 at reset clock operating time. CONSTITUTION:A transistor T2 is turned 'ON' by a pulse of positive voltage applied to a clock terminal 3, and the voltage of a terminal 5 is set at a reset voltage value V2 given to a reset voltage terminal 4. The terminal 5 becomes V1 before V2 by a capacitive capacity between the gate and the source of a transistor T1 and a clock applied to the terminal 3. At this time, a low voltage is applied to a reference voltage clock terminal 10. Thus, since transistors T6, T5 are turned 'OFF', a transistor T4 becomes 'OFF', and a terminal 7 becomes a floating state. Thus, since the source follow is turned 'OFF', power consumption may be small.
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