发明名称 FLOATING GATE VERTICAL FET.
摘要 A planar field effect transistor (FET) includes a plurality of spaced-apart, floating Schottky barrier, epitaxial metal gate electrodes which are embedded within a semiconductor body. A drain electrode and a gate control electrode are formed on one major surface of the body whereas a source electrode, typically grounded, is formed on an opposite major surface of the body. The FET channel extends vertically between the source and drain, and current flow therein is controlled by application of suitable gate voltage. Two modes of operation are possible: (1) the depletion regions of the control gates and the floating gates pinch off the channel so that with zero control gate voltage no current flows from source to drain; then, forward biasing the control gate opens the channel; and (2) the depletion regions of the control gates and the floating gates do not pinch off the channel, but reverse biasing the control gate produces pinch off. Specifically described is a GaAs FET in which the floating gate electrodes are Al epitaxial layers grown by molecular beam epitaxy.
申请公布号 EP0031377(A4) 申请公布日期 1983.04.25
申请号 EP19800901523 申请日期 1981.01.26
申请人 WESTERN ELECTRIC COMPANY, INCORPORATED 发明人 CHO, ALFRED YI
分类号 H01L29/417;H01L21/203;H01L21/285;H01L21/338;H01L29/47;H01L29/80;H01L29/812;H01L29/872;(IPC1-7):H01L29/48;H01L29/161;H01L29/78;H01L29/06;H01L29/04 主分类号 H01L29/417
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