| 摘要 |
PURPOSE:To improve the degree of margin for the input of read data to a processor, by starting the memory read at the timing of address determination independently of the read/write memory cycle. CONSTITUTION:At the timing of the fall of a processor clock PCLK, an upper address is sen to address busses A15-A8, and a lower address is sent to address data busses AD7-AD0. Simultaneously, an address latch enable signal ALE is given to a memory controller 4 to output a line address strobe signal inverted RAS, a column signal inverted COL, and a column address strobe signal inverted CAS. As the result, read data is outputted from a dynamic memory 2 to busses AD7-AD0. In the write cycle, the memory 2 opens the output gate at the time point when the signal inverted CAS is given to the memory 2. Thereafter, when a write control signal inverted WR falls, a write enable signal inverted WE falls, and data is written in the memory 2. |
