Flexible I/O partition of multi-die memory solution

摘要

A method of testing a microelectronic package configured to provide memory access can include energizing terminals of the microelectronic package, the terminals including first terminals configured to carry address information and second terminals configured to carry data signals. The method can also include applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in first and second microelectronic elements of the microelectronic package. The first and second microelectronic elements can be configured to provide access to memory storage array locations in the first and second microelectronic elements. The terminals can also include third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements.

主权项

1. A method of testing a microelectronic package configured to provide memory access, comprising:
energizing terminals of the microelectronic package, the microelectronic package having first and second microelectronic elements each having memory storage array function and configured to provide access to memory storage array locations in the first and second microelectronic elements,
the terminals including a plurality of first terminals configured to carry address information, a plurality of second terminals configured to carry data signals, and one or more third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements, the energizing including applying the test mode input to the one or more third terminals, andthe second terminals including a first set of second terminals electrically coupled to the first microelectronic element and not to the second microelectronic element, and a second set of second terminals electrically coupled to the second microelectronic element and not to the first microelectronic element; and while the test mode input is active, applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in each of the first and second microelectronic elements.