发明名称 Semiconductor device, and display device and electronic device utilizing the same
摘要 A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
申请公布号 US9640135(B2) 申请公布日期 2017.05.02
申请号 US201514941739 申请日期 2015.11.16
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kimura Hajime;Shionoiri Yutaka
分类号 G09G5/00;G09G3/36;H03K19/0185;H01L27/12 主分类号 G09G5/00
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A display device comprising: a pixel portion and a gate line driver circuit over a substrate, wherein the gate line driver circuit is electrically connected to the pixel portion, wherein the gate line driver circuit comprises: a first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a sixth transistor;a seventh transistor; andan eighth transistor, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have same polarity, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor, wherein the one of the source and the drain of the fourth transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor, wherein a gate of the second transistor is electrically connected to a gate of the fifth transistor, wherein a gate of the fourth transistor is configured to be supplied with a first signal, wherein the gate of the fifth transistor is configured to be supplied with a second signal, wherein the one of the source and the drain of the first transistor is configured to output a third signal, wherein one of a source and a drain of the sixth transistor is electrically connected to the one of the source and the drain of the first transistor, wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor, and wherein the one of the source and the drain of the seventh transistor is electrically connected to a gate of the sixth transistor.
地址 Atsugi-shi, Kanagawa-ken JP