GOA circuit based on LTPS semiconductor TFT

摘要

The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400), a pull-down holding part (500) and a transfer part (600); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third DC constant low voltage levels (VSS1, VSS2, VSS3) which are sequentially abated and a DC constant high voltage level (H), the influence of electrical property of the LTPS semiconductor TFT to the GOA driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level the pull-down holding circuit part in the GOA circuit based on the LTPS semiconductor TFT cannot be at higher voltage level in the functioning period can be solved to effectively maintain the first node (Q(N)) and the output end (G(N)) at low voltage level.

主权项

1. A GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected to form a multiple-stage connection structure of the GOA units, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part, a pull-up part, a first pull-down part, a pull-down holding part and a transfer part;
the pull-up control part comprises a first transistor, and a gate of the first transistor is electrically coupled to a driving output end of an N−1th GOA unit which is an immediate former stage of the Nth GOA unit and a source of the first transistor is electrically coupled to an output end of an N−1th GOA unit which is the immediate former stage of the Nth GOA unit, and a drain of the first transistor is electrically coupled to a first node; the pull-up part comprises a second transistor, and a gate of the second transistor is electrically coupled to the first node, and a source of the second transistor is electrically coupled to a first clock driving signal, and a drain of the second transistor is electrically coupled to an output end of the Nth GOA unit; the pull-down holding part is electrically coupled to the first node, the output end, a DC constant high voltage level source, and a first, a second and a third DC constant low voltage sources; the pull-down holding part comprises: a third transistor, and both a gate and a source of the third transistor are electrically coupled to the DC constant high voltage level, and a drain of the third transistor is electrically coupled to a source of a fifth transistor; a fourth transistor, and a gate of the fourth transistor is electrically coupled to the drain of the third transistor, and a source of the fourth transistor is electrically coupled to the DC constant high voltage level, and a drain of the fourth transistor is electrically coupled to a second node; the fifth transistor, and a gate of the fifth transistor is electrically coupled to the first node, and the source of the fifth transistor is electrically coupled to the drain of the third transistor, and a drain of the fifth transistor is electrically coupled to the first DC constant low voltage level; a sixth transistor, and a gate of the sixth transistor is electrically coupled to the first node, and a source of the sixth transistor is electrically coupled to the second node, and a drain of the sixth transistor is electrically coupled to a gate of an eighth transistor; a seventh transistor, and a gate of the seventh transistor is electrically coupled to the first node, and a source of the seventh transistor is electrically coupled to the second node, and a drain of the seventh transistor is electrically coupled to a source of the eighth transistor; the eighth transistor, and the gate of the eighth transistor is electrically coupled to the drain of the sixth transistor, and the source of the eighth transistor is electrically coupled to the drain of the seventh transistor, and a drain of the eighth transistor is electrically coupled to the third DC constant low voltage level; a tenth transistor, and a gate of the tenth transistor is electrically coupled to the second node and a source of the tenth transistor is electrically coupled to the DC constant high voltage level, and a drain of the tenth transistor is electrically coupled to the drain of the seventh transistor; a twelfth transistor, and a gate of the twelfth transistor is electrically coupled to the second node, and a source of the twelfth transistor is electrically coupled to the first node, and a drain of the twelfth transistor is electrically coupled to the second DC constant low voltage level; a thirteenth transistor, and a gate of the thirteenth transistor is electrically coupled to the second node, and a source of the thirteenth transistor is electrically coupled to the output end, and a drain of the thirteenth transistor is electrically coupled to the first DC constant low voltage level; the eighth transistor constructs a reverse bootstrap of negative voltage level in a functioning period of the Nth GOA unit to provide the third lower voltage level to the second node in the functioning period of the Nth GOA unit; the DC constant high voltage level is provided to the second node in a non-functioning period of the Nth GOA unit to maintain the first node and the output end at low voltage level; the first pull-down part is electrically coupled to the first node, a second clock driving signal and the second DC constant low voltage level, and the pull-down part pulls down a voltage level of the first node to the second DC constant low voltage level according to the second clock driving signal; the first pull-down part comprises a fourteenth transistor, and a gate of the fourteenth transistor is electrically coupled to the second clock driving signal, and a source of the fourteenth transistor is electrically coupled to the first node, and a drain of the fourteenth transistor is electrically coupled to the second DC constant low voltage level; the transfer part comprises a fifteenth transistor, and a gate of the fifteenth transistor is electrically coupled to the first node, and a source of the fifteenth transistor is electrically coupled to the first clock driving signal, and a drain of the fifteenth transistor is electrically coupled to a driving output end of the Nth GOA unit; the third DC constant low voltage level