Managing cache memory in a parallel processing environment

摘要

An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

主权项

1. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor; andswitching circuitry including a switch to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; a protection system that comprises:
a storage device storing a minimum protection level value for one or more protected resources within the integrated circuit, with the value being the minimum protection level that is needed to complete a desired action using one of the one or more protected resources without causing a fault; andone or more storage devices storing current protection levels that indicate current protection levels of corresponding portions of a tile, which portions of the tile configured to perform actions using the one or more protected resources, with the protection system configured to:compare the minimum protection level value associated with the resource with the current protection level value of a portion of the tile taking a desired action, and when the minimum protection level is greater than the current protection level value, the protection system causes a fault to occur and generates an interrupt.