Partial access mode for dynamic random access memory

摘要

Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. Although active power increases by a factor of 2N, the refresh time increases by more than 2N as a consequence of the fact that the majority decision does better than averaging for the tail distribution of retention time. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required.

主权项

1. A device comprising:
a plurality of memory banks; a controller controlling storage of data in cells of the plurality of memory banks; a command decoder configured to provide an enable signal responsive to a partial access mode entry command signal; a partial access mode code decoder configured to receive the enable signal, to receive a portion of address signals responsive to the enable signal, to convert the portion of the address signals into a plurality of code flag signals, and further configured to provide a copy operation control signal and the plurality of code signals; and an address decoder circuit coupled to the controller, the address decoder circuit comprising:
at least one multi-bit decoding circuit comprising a plurality of switches, the plurality of switches including comprising a switch configured to select a plurality of word lines; anda delay circuit configured to receive the portion of address signals and the copy operation control signal, and further configured to provide a delay signal when the copy operation control signal is active, wherein the controller copies each bit of data stored in the plurality of memory banks that is to be preserved from 1 cell per bit to a plurality of cells per bit by a copy operation from the 1 cell connected with one word line to the plurality of cells connected with a plurality of respective word lines, wherein the switch is configured to receive a corresponding code flag signal of the plurality of code flag signals and further configured to simultaneously select the plurality of word lines responsive to the corresponding code flag signal, and wherein the switch is further configured to delay selection of the plurality of word lines responsive to the portion of address signals, further responsive to the corresponding code flag signal and the delay signal.