| 发明名称 | Secure switch assembly | ||
| 摘要 | A secure switch assembly is provided and includes inputs respectively associated with at least first and second security levels, switch element outputs respectively associated with the at least first and second security levels and a field programmable gate array (FPGA) operably interposed between the inputs and the switch element outputs. The FPGA has a first side facing the inputs and a second side facing the switch element outputs and includes a gate array. The gate array is programmable to generate entirely separate physical interconnections extending from the first side to the second side by which each of the first security level associated inputs and switch element outputs are connectable and each of the second security level associated inputs and switch element outputs are connectable. | ||
| 申请公布号 | US9641176(B2) | 申请公布日期 | 2017.05.02 |
| 申请号 | US201514804851 | 申请日期 | 2015.07.21 |
| 申请人 | RAYTHEON COMPANY | 发明人 | Hammond Matthew L.;Cramer Norman W.;Kressig, II Robert G. |
| 分类号 | G06F12/14;H03K19/003;H03K19/177 | 主分类号 | G06F12/14 |
| 代理机构 | Cantor Colburn LLP | 代理人 | Cantor Colburn LLP |
| 主权项 | 1. A secure switch assembly, comprising: inputs respectively associated with at least first and second security levels; switch element outputs respectively associated with the at least first and second security levels; and a field programmable gate array (FPGA) operably interposed between the inputs and the switch element outputs, the FPGA having a first side facing the inputs and a second side facing the switch element outputs and comprising a gate array that is programmable to generate entirely separate physical interconnections extending from the first side to the second side by which: each of the first security level associated inputs and switch element outputs are connectable, and each of the second security level associated inputs and switch element outputs are connectable. | ||
| 地址 | Waltham MA US | ||