Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors

摘要

A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

主权项

1. A method for simulating an integrated circuit (IC) design in a circuit design simulator, the method comprising:
receiving data representing a circuit design, said data configured for input to and processing by said circuit design simulator, said data specifying an uplift switch value for an integrated circuit quiescent current (IDDQ) prediction macro, said switch value corresponding to one of: said device, cell, circuit, or IC chip level of design being simulated; when simulating said circuit, using said IDDQ prediction macro to model a leakage current prediction for said circuit design, said leakage current prediction determinable at a device, cell, circuit, or IC chip level of said design, automatically calculating one or more uplift factors representing device variation effects for use in said leakage current prediction model according to the switch value, an uplift factor being a function of a statistical quantity σlpoly of the polysilicon gate length variation of a transistor, a statistical quantity σvtsat of the transistor saturation threshold voltage variation, and a statistical quantity σsubx of the transistor sub-threshold slope, wherein for a specified uplift factor switch value, σlpoly=σACLV; σvtsat is calculated as a function of a statistical quantity σVthRDF defining a 1-sigma Random-Dopant-Fluctuation Induced Vth Variation, and σsubx is calculated as a function of a statistical quantity σsubVth defining a 1-sigma subVth Slope Variation, where Vth is the threshold voltage of the transistor device, and σACLV is a 1-sigma Across-Chip Lpoly Length Variation value due to within chip Across-Chip-Length-Variation, wherein a processor device performs at least one of said receiving, using, modeling and uplift factor calculating.