Semiconductor device and electronic device with data voltages read accurately without the influence of threshold voltage variation

摘要

To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.

主权项

1. A semiconductor device comprising a memory cell, a first wiring, and a second wiring,
wherein the memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor, wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring, wherein the memory cell includes a first data retention portion where the second capacitor, one of a source and a drain of the second transistor, and one of a source and a drain of the fourth transistor are electrically connected to one another, wherein the memory cell includes a second data retention portion where the first capacitor, a gate of the first transistor, the other of the source and the drain of the second transistor, and one of a source and a drain of the third transistor are electrically connected to one another, wherein a first data voltage is configured to be written to the first data retention portion from the first wiring through the first transistor, the second wiring, and the other of the source and the drain of the fourth transistor, and wherein a second data voltage is configured to be written to the second data retention portion from the second wiring through the first transistor, the first wiring, and the other of the source and the drain of the third transistor.