Parity protection of a register

摘要

The embodiments herein generate parity check data which serves as parity-on-parity. Stated differently, the parity check data can be used to determine if parity data stored in a memory element has been corrupted. For example, after generating the parity data, a computing system may set the parity check data depending on whether there is an even or odd number of logical ones (or logical zeros) in the parity data. Thus, when the parity data is read out of the memory element, if the parity data does not include the same number of even or odd bits, the parity check data indicates to the computing system that the parity data is corrupted. In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements.

主权项

1. An integrated circuit, comprising:
a memory comprising a plurality of registers, each register comprising:
a data entry, anda parity entry, a plurality of latches distinct from the plurality of registers; logic configured to:
in response to receiving a write request to a first register of the plurality of registers, generate parity data based on data corresponding to the write request,store the data corresponding to the write request and the parity data in the first register,generate parity check data based on the parity data, wherein the parity check data, when compared with the parity data, indicates whether a soft error is introduced in the parity data when stored in the first register, andstore the parity check data in a first latch of the plurality of latches.