| 摘要 |
A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode. |
| 主权项 |
1. A processor core configured to carry out data processing operations in dependence on a sequence of data processing instructions, the processor core comprising:
a front end, a first back end and a second back end, the front end comprising a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends each configured to execute the sequence of program instructions, wherein the processor core is configured to operate in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and the processor core is configured to operate in a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, wherein an average cycles-per-instruction rate is lower and an energy consumption is higher for the first mode than the second mode, and the processor core further comprises a performance controller configured to control whether the processor core operates in the first mode or the second mode to thereby satisfy a predetermined metric which counterbalances the energy consumption and the cycles-per-instruction rate, wherein the performance controller comprises a performance estimator configured, when the processor core is in the first mode, to generate an estimated cycles-per-instruction rate of the processor core over a predetermined interval if the processor had been in the second mode, and configured, when the processor core is in the second mode, to generate the estimated cycles-per-instruction rate of the processor core over the predetermined interval if the processor had been in the first mode. |
