Thermal-aware compiler for parallel instruction execution in processors

摘要

Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.

主权项

1. A method for compiling instruction code for execution in a processor having a plurality of computing stages, each having a plurality of functional units, comprising:
determining a thermal constraint of the computing stages of the processor; and scheduling in the compiled instruction code real instructions to be executed in parallel by first functional units of a first computing stage by a first very long instruction word (VLIW), and second functional units of a second computing stage by a second VLIW, wherein the first functional units are different from the second functional units, and further wherein the scheduling is configured to prevent exceeding the thermal constraint during execution of the instruction code; inserting a first set of no operation (NOP) instructions with the real instructions executed by the first functional units and second set of NOP instructions with the real instructions executed by the second functional units to create interleaved NOP instructions between two consecutive instruction words; and counting continuous NOP instructions of the first and second set of NOP instructions; determining if a number of continuous NOP instructions exceeds a threshold and if so, shutting down one of the first functional unit or second functional unit and clearing the counter upon receipt of a next real instruction.