| 发明名称 | Common N-well state retention flip-flop | ||
| 摘要 | Embodiments include apparatuses, methods, and systems for state retention electronic devices. In embodiments, an electronic device may include a state retention flip-flop having a plurality of P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, with one or more of the plurality of PMOS devices powered by an always-on supply and one or more of the plurality of PMOS devices powered by a power-gated supply. Other embodiments may be described and claimed. | ||
| 申请公布号 | US9641160(B2) | 申请公布日期 | 2017.05.02 |
| 申请号 | US201514635849 | 申请日期 | 2015.03.02 |
| 申请人 | Intel Corporation | 发明人 | Agarwal Amit;Hsu Steven;Krishnamurthy Ram |
| 分类号 | H03K3/356;H03K3/3562;H03K3/012;H03K3/037 | 主分类号 | H03K3/356 |
| 代理机构 | Schwabe, Williamson & Wyatt, P.C. | 代理人 | Schwabe, Williamson & Wyatt, P.C. |
| 主权项 | 1. An electronic device comprising: a state retention flip-flop including P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, wherein one or more of the PMOS devices coupled with the common N-well are powered by an always-on supply and one or more of the PMOS devices coupled with the common N-well are powered by a power-gated supply. | ||
| 地址 | Santa Clara CA US | ||