Techniques for managing graphics processing resources in a tile-based architecture

摘要

One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released.

主权项

1. A computer-implemented method for managing buffer table entries, the method comprising:
binding a plurality of shader registers to a first buffer table entry included in a buffer table, wherein each shader register included in the plurality of shader registers stores an index to the first buffer table entry included in the buffer table; for each shader register included in the plurality of shader registers, processing at least one tile included in a plurality of tiles by:
reading the index stored in the shader register to access the first buffer table entry;reading a first buffer address stored in the first buffer table entry and associated with a first buffer memory;reading data from or writing data to the first buffer memory based on the first buffer address; andunbinding the shader register from the first buffer table entry; determining, by a cache controller, that none of the shader registers included in the plurality of shader registers is still bound to the first buffer table entry; in response to determining that none of the shader registers is still bound, causing a release packet to be inserted into an instruction stream transmitted to a tiling unit; determining, by the tiling unit, that a last tile included in the plurality of tiles has been processed; in response to determining that the last tile has been processed, transmitting the release packet to a specified processing unit in a screen-space pipeline; and causing the first buffer table entry to be released in response to the specified processing unit receiving the release packet.