| 发明名称 |
MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS |
| 摘要 |
One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor. |
| 申请公布号 |
US2017115716(A1) |
申请公布日期 |
2017.04.27 |
| 申请号 |
US201615238717 |
申请日期 |
2016.08.16 |
| 申请人 |
Intel Corporation |
发明人 |
VARMA ANKUSH;SISTLA KRISHNAKANTH V.;ROWLAND MARTIN T.;POIRIER CHRIS;DEHAEMER ERIC J.;ANANTHAKRISHNAN AVINASH N.;SHRALL JEREMY J.;MAN XIUTING C.;GUNTHER STEPHEN H.;RANGAN KRISHNA K.;BODAS DEVADATTA V.;SOLTIS DON;NGUYEN HANG T.;WOO CYPRIAN W.;DANG THI |
| 分类号 |
G06F1/28;G06F1/20 |
主分类号 |
G06F1/28 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a semiconductor chip having a processor and on-die non-volatile storage, said on-die non-volatile storage to store different, performance related information for different configurations and expected usage cases of said processor for a same performance state of said processor, and circuitry to detect a configuration change to the processor and provide an operating performance level to the processor from the different, performance related information. |
| 地址 |
Santa Clara CA US |
