发明名称 TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL
摘要 In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.
申请公布号 US2017115338(A1) 申请公布日期 2017.04.27
申请号 US201615336687 申请日期 2016.10.27
申请人 NVIDIA CORPORATION 发明人 Chadalavda Sailendra;Sarangi Shantanu;Sonawane Milind;Sanghani Amit;Colburn Jonathon E.;Smith Dan;Wu Jue;Yilmaz Mahmut
分类号 G01R31/28 主分类号 G01R31/28
代理机构 代理人
主权项 1. A chip test system comprising: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations.
地址 Santa Clara CA US