Feedback control system with rising and falling edge detection and correction

摘要

A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.

主权项

1. A feedback control system comprising:
a controllable oscillator configured to generate an output clock signal based on at least one control signal generated using at least one error signal; and an error detector configured to generate the at least one error signal based on a rising edge difference between a rising edge of an input clock signal and a first corresponding edge of an edge alignment corrected feedback clock signal and further based on a falling edge difference between a falling edge of the input clock signal and a second corresponding edge of the edge alignment corrected feedback clock signal, wherein the edge alignment corrected feedback clock signal is at least partially based on the output clock signal.