发明名称 MOSFET and method for manufacturing the same
摘要 The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate.
申请公布号 US9633854(B2) 申请公布日期 2017.04.25
申请号 US201113379433 申请日期 2011.08.02
申请人 Institute of Microelectronics, Chinese Academy of Sciences 发明人 Zhu Huilong;Xu Miao;Liang Qingqing
分类号 H01L29/78;H01L21/265;H01L29/66;H01L29/786;H01L21/26 主分类号 H01L29/78
代理机构 Westman, Champlin & Koehler, P.A. 代理人 Westman, Champlin & Koehler, P.A.
主权项 1. A MOSFET, comprising: an SOI wafer comprising a semiconductor substrate, a buried insulating layer and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region; wherein: the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate and isolated from the channel region by the buried insulating layer, the counter doped region is disposed under and aligned to the channel region and embedded in the back gate and adjoins the back gate on opposite sides of the counter doped region, and the back gate has a doping type opposite to that of the counter doped region;the counter doped region is shorter than a gate length and is isolated from the channel region by the buried insulating layer;below the channel region, the back gate has a doping concentration which gradually decreases laterally towards a center of the channel region; anda portion of the back gate that is not under the channel region has a higher doping concentration than a portion of the back gate that is under the channel region.
地址 Beijing CN