| 主权项 |
1. A circuit comprising:
one or more nodes for providing a clock signal; a first stage of circuit elements comprising first Clock Guided Logic (CGL) elements in a pipelined configuration from an initial first CGL element to a final first CGL element;
wherein a first clock path of the first stage is coupled to the one or more nodes to receive the clock signal, the first clock path further coupled to a second input of each first CGL element and configured to provide first guide signals to the second inputs of the first CGL elements to drive the first CGL elements into pre-charge and evaluate phases; a second stage of circuit elements comprising second CGL elements in a pipelined configuration from an initial second CGL element to a final second CGL element;
wherein a second clock path of the second stage is coupled to a second input of each second CGL element and configured to provide second guide signals to the second inputs of the second CGL elements to drive the second CGL elements into pre-charge and evaluate phases; a first latch coupled to the first stage such that an input of the first stage is coupled to a data output of the first latch;
wherein a third clock path is coupled to the one or more nodes to receive the clock signal, the third clock path further coupled to a first clock input of the first latch and configured to provide the clock signal to the first clock input to open and close the first latch, the first latch configured to open during a first phase of the clock signal and to close during a second phase of the clock signal; a second latch coupled to the first stage and to the second stage such that an output of the first stage is coupled to a data input of the second latch, and such that a data output of the second latch is coupled to an input of the second stage;
wherein a fourth clock path is coupled to the one or more nodes to receive the clock signal, the fourth clock path further coupled to a second clock input of the second latch and configured to provide an input clock signal to the second clock input to open and close the second latch, the input clock signal having an inverted relationship with the clock signal such that the second latch is closed when the first latch is open and is open when the first latch is closed; and a guide logic gate coupling the first clock path of the first stage to the second clock path of the second stage;
wherein a first input of the guide logic gate is coupled to the first clock path such that the first input of the guide logic gate is coupled to a second input of the final first CGL element;wherein a second input of the guide logic gate is coupled to the one or more nodes to receive the clock signal; andwherein an output of the guide logic gate is coupled to the second clock path such that the output of the guide logic gate is coupled to a second input of the initial second CGL element to drive the initial second CGL element into pre-charge and evaluate phases. |
