Apparatus, system and method for a common unified debug architecture for integrated circuits and SoCs

摘要

A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.

主权项

1. An apparatus comprising:
an integrated circuit including,
a display port;a plurality of logic blocks;debug logic to receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit operating in a debug mode;control logic coupled to at least the debug logic, the control logic to provide display data to the display port at a first frequency in response to the integrated circuit operating in an operational mode and to direct high-speed debug data to the display port in response to the integrated circuit operating in the debug mode, wherein the high-speed debug data is to be based on the debug data; anda General Purpose Input/Output (GPIO) port which is responsive to the control logic and may receive debug data from the control logic at a second frequency when the integrated circuit is operating in the debug mode.