发明名称 |
Providing input/output virtualization (IOV) by mapping transfer requests to shared transfer requests lists by IOV host controllers |
摘要 |
An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI. |
申请公布号 |
US9632953(B2) |
申请公布日期 |
2017.04.25 |
申请号 |
US201514728343 |
申请日期 |
2015.06.02 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Shacham Assaf;Raviv Dolev;Teb David |
分类号 |
G06F12/00;G06F13/16;G06F3/06 |
主分类号 |
G06F12/00 |
代理机构 |
Withrow + Terranova, PLLC |
代理人 |
Withrow + Terranova, PLLC |
主权项 |
1. An input/output virtualization (IOV) host controller (HC) (IOV-HC) communicatively coupled to a plurality of input/output (I/O) clients via a corresponding plurality of client register interfaces (CRIs), and to a flash-memory-based storage device;
the IOV-HC comprising:
a plurality of transfer request list (TRL) slot offset registers, each indicating a slot of a shared TRL that is assigned as a base slot to each CRI of the plurality of CRIs; anda plurality of TRL slot count registers, each indicating a number of slots of the shared TRL assigned to each CRI of the plurality of CRIs; and the IOV-HC configured to:
receive a transfer request (TR) directed to the flash-memory-based storage device from a CRI of the plurality of CRIs; andmap, by a TR fetch circuit of the IOV-HC, the TR to a slot of the shared TRL based on a TRL slot offset register of the plurality of TRL slot offset registers and a TRL slot count register of the plurality of TRL slot count registers, the TRL slot offset register and the TRL slot count register corresponding to the CRI. |
地址 |
San Diego CA US |