发明名称 Methods and systems for time keeping in a data processing system
摘要 Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.
申请公布号 US9632563(B2) 申请公布日期 2017.04.25
申请号 US201414159705 申请日期 2014.01.21
申请人 Apple Inc. 发明人 de Cesare Joshua P.;Semeria Bernard Joseph;Smith Michael John
分类号 G06F13/36;G06F1/32;G06F9/48;G06F13/24 主分类号 G06F13/36
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
主权项 1. A system, comprising: a memory configured to store a plurality of application programs; a processing unit configured to: determine a time latency value for the processing unit to power up from a reduced power state;determine a wake up time for a timed event for a given one of the stored plurality of application programs dependent upon the determined time latency value and a scheduled time for processing the timed event; andenter the reduced power state;and a timer unit configured to assert, for the given one of the stored plurality of application programs, an interrupt of a first type at the determined wake up time; and wherein the processing unit is further configured to: in response to a determination that interrupts are disabled, convert the interrupt of the first type to an interrupt of a second type; andexit the reduced power state in response to a determination that the interrupts have been enabled.
地址 Cupertino CA US