Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout

摘要

Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.

主权项

1. A Field-Effect Transistor (FET) cell having an asymmetric gate width layout, comprising:
a substrate comprising a body having a top surface; a FET device, comprising:
a source disposed in the substrate;a drain disposed in the substrate; andan active gate of an active gate width formed between the source and the drain; and an isolation structure disposed in the substrate adjacent to the FET device, the isolation structure comprising:
a diffusion break disposed in the substrate adjacent to one of the source and the drain of the FET device, wherein a depth of the one of the source and the drain that is adjacent to the diffusion break is greater than a depth of the one of the source and the drain that is not adjacent to the diffusion break; anda dummy gate of a dummy gate width formed above the diffusion break adjacent to the active gate, the dummy gate width being smaller than the active gate width by a gate width margin.