发明名称 |
Demodulator apparatus and demodulation method |
摘要 |
A demodulator apparatus includes a memory and a processor coupled to the memory. The processor executes a process including: applying lattice reduction to a channel response matrix; applying linear detection to a reception signal in lattice-reduced basis using a lattice-reduced channel response matrix; calculating an expectation of a symbol in the lattice-reduced basis; inversely transforming the expectation of the symbol from the lattice-reduced basis into an original basis; and calculating soft-decision data by performing interference cancellation method in inversely transformed expectation of the symbol in the original basis. |
申请公布号 |
US9634879(B2) |
申请公布日期 |
2017.04.25 |
申请号 |
US201615003338 |
申请日期 |
2016.01.21 |
申请人 |
FUJITSU LIMITED |
发明人 |
Miyazaki Shunji |
分类号 |
H04B1/66;H04L27/38;H04L27/34 |
主分类号 |
H04B1/66 |
代理机构 |
Fujitsu Patent Center |
代理人 |
Fujitsu Patent Center |
主权项 |
1. A demodulator apparatus comprising:
a plurality of antennas; a memory; and a processor coupled to the plurality of antennas and the memory, wherein the processor executes a process comprising: receiving signal via each of the plurality of antennas; applying lattice reduction to a channel response matrix calculated by using the received signal; applying linear detection to the received signal in lattice-reduced basis using a lattice-reduced channel response matrix; first calculating an expectation of a symbol in the lattice-reduced basis; inversely transforming the expectation of the symbol from the lattice-reduced basis into an original basis; second calculating soft-decision data by performing interference cancellation method in inversely transformed expectation of the symbol in the original basis; and outputting bits obtained by performing an error correcting decoding process using the soft-decision data. |
地址 |
Kawasaki JP |