发明名称 Transmitter with a reduced complexity digital up-converter
摘要 The present disclosure is directed to a system and method for performing digital up-conversion of a signal to a desired RF carrier frequency. The system and method efficiently perform digital up-conversion of the signal, in one example, by controlling a sample clock that is used by a DAC to sample and convert the up-converted signal from the digital domain to the analog domain to have a frequency that is four or eight times the desired RF carrier frequency. By controlling the sample clock of the DAC to have a frequency that is four or eight times the desired RF carrier frequency, the system and method can be implemented using currently available IC process geometries such that the implementation consumes much less area and/or power than an analog up-converter configured to have equivalent up-conversion functionality.
申请公布号 US9634694(B2) 申请公布日期 2017.04.25
申请号 US201414163783 申请日期 2014.01.24
申请人 Avago Technologies General IP (Singapore) Pte. Ltd. 发明人 Harris David Money;Garrett David;Lorenz Bob
分类号 H04B1/04;H04B1/66;H04B1/02;H04B1/00 主分类号 H04B1/04
代理机构 Sterne, Kessler, Goldstein & Fox P.L.L.C. 代理人 Sterne, Kessler, Goldstein & Fox P.L.L.C.
主权项 1. A transmitter comprising: a sample clock generator configured to generate a sample clock to have a frequency that is 4, 8, or 8/3 times a carrier frequency plus an offset frequency; an intermediate frequency (IF) digital frequency-shifter configured to frequency-shift a baseband signal by the offset frequency divided by 4, 8, or 8/3 to provide an IF signal; a radio frequency (RF) digital up-converter configured to up-convert the IF signal to provide a digital RF signal at the carrier frequency; and a digital-to-analog converter (DAC) configured to sample the digital RF signal using the sample clock and convert the samples of the digital RF signal to an analog RF signal for transmission over a channel.
地址 Singapore SG