Cache for patterns of instructions with multiple forward control transfers

摘要

Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

主权项

1. An apparatus, comprising:
an instruction cache; and control circuitry configured to:
detect a pattern of execution of instructions, wherein the instructions are a set of instructions executed by an instruction processing pipeline, based on execution of at least a portion of the instructions in the set of instructions multiple times, wherein the pattern includes multiple forward control transfer instructions within a loop;
wherein at least one of the multiple forward control transfer instructions, during a time interval between detecting the pattern and exiting the pattern, transfers control in one iteration of the pattern and does not transfer control in another iteration of the pattern; andwherein at least one cache line between at least one of the multiple forward control transfer instructions and its target is not included in the pattern; andstore the set of instructions in the instruction cache, wherein the apparatus is configured to store at most one copy of each instruction in the pattern in the stored set of instructions; wherein the apparatus is configured to fetch and execute the instructions from the instruction cache.