Stacked semiconductor package and manufacturing method thereof

摘要

A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles.

主权项

1. A stacked semiconductor package, comprising:
a lower semiconductor package, comprising:
a substrate;a semiconductor chip attached to a center region of an upper surface of the substrate;a plurality of terminals attached to and extending upward from a peripheral region of the upper surface of the substrate around the center region; anda molding compound covering the upper surface of the substrate, at least a portion of side surfaces of the semiconductor chip, and at least a portion of a side surface of each of the terminals,wherein at least an upper surface of each of the terminals is exposed from the molding compound; and an interposer comprising a plurality of contacts on a lower surface; and an adhesive member bonding the lower surface of the interposer to an upper surface of the lower semiconductor package, wherein the adhesive member comprises conductive particles that conductively couple each of the terminals of the lower semiconductor package and a respective one of the interposer contacts, and wherein the adhesive member directly contacts side surfaces of the interposer contacts.