Shift register

摘要

A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.

主权项

1. A shift register comprising a plurality of unit circuits connected in multiple stages, wherein
the unit circuit includes: an output transistor having a first conduction terminal connected to a clock terminal for inputting a clock signal, and a second conduction terminal connected to an output terminal for outputting the clock signal; an output control unit that applies an on-potential and an off-potential in a switching manner to a control terminal of the output transistor; and an initialization transistor having a first conduction terminal connected to the control terminal of the output transistor, and a control terminal provided with an initialization signal, and a second conduction terminal of the initialization transistor is connected to a node which has the off-potential at the time of initialization and has the on-potential at the same level as the clock signal when the clock signal having the on-potential is outputted from the output terminal.