Non-preemption of a group of interchangeable tasks in a computing device

摘要

A non-preemption task group apparatus comprises a scheduling module that identifies a first task that is one of executing and scheduled to execute on a processor during a first time slice and a second task to be executed on a processor during a subsequent time slice, the first slice occurring before the subsequent slice, a relationship module that compares the first task to the second task, and an examining module that identifies whether the first task and the second task are interchangeable tasks based on the comparison, wherein the first task executes during the subsequent time slice in response to the first task and the second task being identified as interchangeable.

主权项

1. An apparatus comprising:
a scheduling module that identifies a first task that is one of executing and scheduled to execute on a processor during a first time slice and a second task scheduled to be executed on the processor during a subsequent time slice immediately adjacent to the first time slice, the first time slice occurring before the subsequent time slice; a relationship module that compares the first task to the second task; an examining module that identifies whether the first task and the second task are interchangeable tasks based on the comparison, wherein interchangeable tasks share context information and belong to a common job; a task queuing module that assigns the first task and the second task to adjacent time slices in response to the first task and the second task being identified as interchangeable tasks; and an interrupt handling module that suppresses delivery of an interrupt signal at the end of the first time slice in response to the first task and the second task being identified as interchangeable tasks, wherein the first task executes during the subsequent time slice in response to the first task and the second task being identified as interchangeable tasks, wherein at least a portion of the scheduling module, the relationship module, the examining module, the task queuing module, and the interrupt handling module comprise one or more of a hardware circuit and program instructions stored on one or more non-transitory computer readable media.