| 发明名称 |
PERIPHERAL CONTROLLER |
| 摘要 |
A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral. |
| 申请公布号 |
US2017109314(A1) |
申请公布日期 |
2017.04.20 |
| 申请号 |
US201615262746 |
申请日期 |
2016.09.12 |
| 申请人 |
NXP B.V. |
发明人 |
NAHVAL VINOD KUMAR |
| 分类号 |
G06F13/42;G06F13/40;G06F5/06 |
主分类号 |
G06F13/42 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A peripheral controller for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, the peripheral controller comprising:
a FIFO including a FIFO controller and a FIFO memory and having a plurality of inputs; and a multiplexer circuit connected to the plurality of inputs, wherein the multiplexer circuit is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral. |
| 地址 |
Eindhoven NL |
