APPARATUS AND METHOD FOR ACCELERATING OPERATIONS IN A PROCESSOR WHICH USES SHARED VIRTUAL MEMORY

摘要

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

主权项

1. A system comprising:
a plurality of simultaneous multithreading (SMT) cores to perform out-of-order instruction execution for a plurality of threads; a memory hierarchy comprising a system memory and a plurality of cache levels coupled to one or more of the SMT cores; an accelerator to perform data operations associated with one or more tasks, the accelerator comprising: an accelerator functional unit; and context save/restore circuitry to save and restore a context of the accelerator functional unit; and front end hardware logic coupled to the accelerator, the front end hardware logic to receive and schedule tasks for execution on the accelerator, the front end hardware logic comprising: a translation lookaside buffer (TLB) to store virtual-to-physical address mappings; and page walker circuitry to provide page walk services to the accelerator to determine virtual-to-physical address mappings.