Test Line Patterns in Split-Gate Flash Technology

摘要

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

主权项

1. An integrated chip, comprising:
a semiconductor substrate; a test line letter arranged over the semiconductor substrate, wherein the test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in a shape of an alpha-numeric character; and one or more dummy structures arranged over the semiconductor substrate and proximate to a boundary of the test line letter.