MEMORY DEVICE AND SYSTEM SUPPORTING COMMAND BUS TRAINING, AND OPERATING METHOD THEREOF

摘要

A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.

主权项

1. A command bus training method in a system in which a command/address signal and a clock signal are provided to a memory device from a memory controller, the command bus training method comprising:
entering into a command bus training mode at the memory device; generating an internal clock signal in the memory device by dividing the clock signal; transmitting a first command/address signal by the memory controller; transmitting a chip selection signal by the memory controller, the chip selection signal having an adjustable delay with respect to the internal clock signal; generating and transmitting by the memory device, a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal, when the chip selection signal is activated; comparing the first command/address signal with the second command/address signal by the memory controller; and determining a delay of the chip selection signal based on a plurality of comparison results corresponding to the adjustable delay of the chip selection signal.