| 摘要 |
The present application relates to the technical field of field bus communication, and in particular to a protocol converter between a CPCI bus and an ISA bus and a conversion method thereof, which are suitable for communication between railway vehicle CPUs and vehicle bus MVB devices. The protocol converter comprises a CPCI local bus interface extension timing module, an ISA bus interface timing module, a CPCI bus matching ISA bus timing interface module, and a clock management module. The CPCI bus realizes communication with the ISA bus by the protocol converter. The traditional conversion bridge chips are replaced with the protocol converters without changing the traction controller structure and other devices in the system; the flexibility is high; and the functions are diverse. In addition, 8-bit data width or 16-bit data width of the ISA bus is supported, and the operation of an ISA bus device by a CPCI bus device in the form of IO or in the form of MEMORY is supported. |
| 主权项 |
1. A protocol converter between a CPCI bus and an ISA bus, characterized in that, the protocol converter comprises a CPCI local bus interface extension timing module, an ISA bus interface timing module, a CPCI bus matching ISA bus timing interface module, and a clock management module;
the CPCI local bus interface extension timing module communicates with the local CPCI bus by an address/data signal AD [31:0], a command/byte enable signal C/BE [3:0], a slave device get-ready signal TRDY, a data transfer stop signal STOP, a frame period signal FRAME, and a master device get-ready signal IRDY; the ISA bus interface timing module communicates with the CPCI local bus interface extension timing module by a data enable signal S_DATA_VLD, an address enable signal ADDR_VLD, a read enable signal barx_rd, a write enable signal barx_wr, a byte enable signal S_CBE, a data signal D [31:0] and an address signal A [31:0]; the ISA bus interface timing module communicates with the local ISA bus by a data signal SD, an address signal SA, a read/write IO device signal IOW/IOR, a read/write MEMORY device signal MEMR/MEMW, an address latch signal BALE; the CPCI bus matching ISA bus timing interface module communicates with the CPCI local bus interface extension timing module by an interruption and reconnection signal USER_STOP; and the clock management module provides an operation clock for the CPCI local bus interface extension timing module, the ISA bus interface timing module and the CPCI bus matching ISA bus timing interface module. |
