HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS

摘要

An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.

主权项

1. An apparatus comprising:
a transmitter comprising logic to:
send an exit pattern to initiate exit from a partial width state, wherein data is to be sent on a link when in the partial width state, a portion of lanes of the link comprise idle lanes and remaining lanes of the link are active in the partial width state, and the exit pattern is sent on the idle lanes, wherein the exit pattern comprises an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp), the SDS comprises a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes, wherein data continues to be sent on the active lanes concurrently with the sending of the exit pattern on the idle lanes;exit the partial width state based on the exit pattern; andsend data on all lanes following the exit from the partial width state.