发明名称 METHOD AND APPARATUS FOR PROCESSING INSTRUCTIONS IN A MICROPROCESSOR HAVING A MULTI-EXECUTION SLICE ARCHITECTURE
摘要 Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.
申请公布号 US2017109171(A1) 申请公布日期 2017.04.20
申请号 US201514883349 申请日期 2015.10.14
申请人 International Business Machines Corporation 发明人 EISEN Susan E.;KUCHARSKI Cliff;LE Hung Q.;NGUYEN Dung Q.;TERRY David R.
分类号 G06F9/38;G06F12/08;G06F9/30 主分类号 G06F9/38
代理机构 代理人
主权项 1. A method for writing a history buffer in a processing unit, comprising: dispatching at least a first instruction and a second instruction in a single processing cycle targeting a same register file entry, wherein the processing unit comprises two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file; determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction; writing the first result data directly into a history buffer bypassing the register file entry, in response to the determination; and writing the second result data into the register file entry.
地址 Armonk NY US