发明名称 DISPLAY DEVICE HAVING IMPROVED ELECTROMAGNETIC INTERFERENCE CHARACTERISTICS
摘要 A display device includes a timing controller configured to receive an image data signal and a plurality of clock signals and to generate a scan clock signal and a plurality of data clock signals, a scan driver configured to receive the scan clock signal, and a data driver configured to receive the data clock signals. The clock signals include first to nth clock signals, and the data clock signals include first to nth data clock signals generated from the first to nth clock signals (n≧2), the first to nth clock signals having differing frequencies and the first to nth data clock signals having differing frequencies. Whenever a predetermined number of frame periods has elapsed, the timing controller halts transmission of one of the first to nth data clock signals to the data driver, and begins transmission of another one of the first to nth data clock signals thereto.
申请公布号 US2017110078(A1) 申请公布日期 2017.04.20
申请号 US201615249095 申请日期 2016.08.26
申请人 Samsung Display Co., Ltd. 发明人 KIM Min Woo;KIM Dong In;GO Seong Hyun;CHOI On Sik
分类号 G09G3/36 主分类号 G09G3/36
代理机构 代理人
主权项 1. A display device comprising: a timing controller configured to receive an image data signal and a plurality of clock signals, and to generate a scan clock signal and a plurality of data clock signals; a scan driver configured to receive the scan clock signal; and a data driver configured to receive the data clock signals, wherein the plurality of clock signals includes first to nth clock signals, and the plurality of data clock signals includes first to nth data clock signals generated from the first to nth clock signals (n is a natural number having a value of 2 or greater), the first to nth clock signals having frequencies different from each other and the first to nth data clock signals having frequencies different from each other, and wherein whenever a predetermined number of frame periods has elapsed, the timing controller halts transmission of one of the first to nth data clock signals to the data driver, and begins transmission of another one of the first to nth data clock signals to the data driver.
地址 Yongin-si KR
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