发明名称 HIGH PERFORMANCE INTERCONNECT
摘要 A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
申请公布号 US2017109315(A1) 申请公布日期 2017.04.20
申请号 US201615393153 申请日期 2016.12.28
申请人 Intel Corporation 发明人 Safranek Robert J.;Blankenship Robert G.;Iyer Venkatraman;Willey Jeff;Beers Robert H.;Jue Darren S.;Kumar Arvind A.;Sharma Debendra Das;Swanson Jeffrey C.;Fahim Bahaa;Geetha Vedaraman;Spink Aaron T.;Spagna Fulvio;Shah Rahul R.;Iyer Sitaraman V.;Nale William Harry;Das Abhishek;Johnson Simon P.;Dhillon Yuvraj S.;Liu Yen-Cheng;Ramanujan Raj K.;Maddox Robert A.;Hum Herbert H.;Gupta Ashish
分类号 G06F13/42;H04L9/06;G06F11/10;G06F13/40 主分类号 G06F13/42
代理机构 代理人
主权项
地址 Santa Clara CA US