发明名称 |
LOAD LOCK INTERFACE AND INTEGRATED POST-PROCESSING MODULE |
摘要 |
A load lock assembly includes a first load lock connected between an equipment front end module (EFEM) and a wafer transport module, the EFEM being at a lab ambient condition, the wafer transport module being at a vacuum condition, the wafer transport module being part of a wafer transport assembly that is configured to transport wafers to and from one or more process modules that are connected to the wafer transport assembly; a second load lock disposed over the first load lock, the second load lock connected between the EFEM and the wafer transport module; a post-processing module disposed over the second load lock, the post-processing module configured for performing a post-processing operation on a processed wafer that has been processed in at least one of the process modules that are connected to the wafer transport assembly, the post-processing module being configured for connection to the wafer transport module. |
申请公布号 |
US2017110351(A1) |
申请公布日期 |
2017.04.20 |
申请号 |
US201514887959 |
申请日期 |
2015.10.20 |
申请人 |
Lam Research Corporation |
发明人 |
Trussell David;Gould Richard;Daugherty John |
分类号 |
H01L21/67;H01L21/673;H01L21/677 |
主分类号 |
H01L21/67 |
代理机构 |
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代理人 |
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主权项 |
1. A load lock assembly, comprising:
a first load lock configured for connection between an equipment front end module (EFEM) and a wafer transport module, the EFEM being maintained at a lab ambient condition, the wafer transport module being maintained at a vacuum condition, the wafer transport module being part of a wafer transport assembly that is configured to transport wafers to and from one or more process modules that are connected to the wafer transport assembly; a second load lock disposed over the first load lock, the second load lock configured for connection between the EFEM and the wafer transport module; a post-processing module disposed over the second load lock, the post-processing module configured for performing a post-processing operation on a processed wafer that has been processed in at least one of the process modules that are connected to the wafer transport assembly, the post-processing module being configured for connection to the wafer transport module. |
地址 |
Fremont CA US |