发明名称 Data output dispatching device and method
摘要 The present invention discloses a data output dispatching device and method capable of reducing the probability of packets from the same queue being transmitted sequentially. An embodiment of the method comprises the following steps: providing a plurality of buffers capable of storing the data of Q queues respectively while each queue is associated with a weighting and the sum Ws of all the weightings is between 2(M-1) and 2M and not greater than a maximum sum in which Q is an integer greater than 1, M is a positive integer and N is an integer not less than M; providing a binary bit reverse count value not greater than 2N; and assigning a token to one of the Q queues for data output according to the reverse count value.
申请公布号 US2017109303(A1) 申请公布日期 2017.04.20
申请号 US201615265450 申请日期 2016.09.14
申请人 Realtek Semiconductor Corporation 发明人 ZHU JIAN-YIN
分类号 G06F13/22;G06F13/37;G06F13/16;G06F5/01 主分类号 G06F13/22
代理机构 代理人
主权项 1. A data output dispatching device configured to reduce a probability that packets from a same queue are transmitted sequentially, the data output dispatching device comprising: Q buffers configured to store data of Q queues respectively while the Q queues are associated with Q weightings respectively and each of the Q weightings is not greater than a maximum weighting which is equal to or less than 2N, in which the Q is an integer greater than one and the N is a positive integer; a weighting allocator configured to allocate the Q weightings according to a binary bit reverse sequence so as to distribute a Kth weighting among the Q weightings and make the Kth weighting be logically associated with T queue point(s) of 2N queue points, in which the K is a positive integer not greater than the Q, the T is an integer not less than zero and not greater than the maximum weighting, the value of the Kth weighting is the T, and the order of the 2N queue points is in incremental order; and a polling circuit configured to poll the Q buffers according to at least a part of the order of the 2N queue points, and when the polling circuit polls the Q buffers during a current polling cycle, the polling circuit allows a buffer of the Q buffers in association with the Kth weighting to obtain a token for data output if the current polling cycle is logically associated with one of the T queue point(s) of the 2N queue points.
地址 Hsinchu TW