| 发明名称 |
MEMORY DEVICE AND SYSTEM SUPPORTING COMMAND BUS TRAINING, AND OPERATING METHOD THEREOF |
| 摘要 |
An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal. |
| 申请公布号 |
US2017110165(A1) |
申请公布日期 |
2017.04.20 |
| 申请号 |
US201615298491 |
申请日期 |
2016.10.20 |
| 申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
KIM Hye-Ran;OH Tae-Young |
| 分类号 |
G11C7/22;G11C8/10;G11C8/18 |
主分类号 |
G11C7/22 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An operating method of a memory device supporting command bus training, the operating method comprising:
entering into a mode of the command bus training; receiving a clock signal, chip selection signal and a first command/address signal; generating a plurality of internal clock signals by dividing the clock signal; generating a plurality of internal chip selection signals by latching the chip selection signal according to the plurality of internal clock signals; generating a second command/address signal by encoding the first command/address signal based on the plurality of internal chip selection signals; and outputting the second command/address signal. |
| 地址 |
Suwon-si KR |
