SLAVE DEVICE ALERT SIGNAL IN INTER-INTEGRATED CIRCUIT (I2C) BUS SYSTEM

摘要

A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

主权项

1. An inter-integrated circuit (I2C) bus system comprising:
at least one master device; and at least one slave device communicating with the master device over a bidirectional two-line I2C bus, the I2C bus having a serial data (SDA) line and a serial clock (SCL) line that are normally high unless a device pulls the voltage of the line low, wherein:
the master device provides clock signals having high and low phases to the SCL line;one of the master and the slave device, as transmitter, sets normal data signals on the SDA line during the low phase of the clock signals on the SCL line and the normal data signals are transferred to the other device, as receiver, during the high phase of the clock signals on the SCL line; andthe slave device provides an alert pulse on the SDA line during the low phase of the clock signals on the SCL line to send an alert signal to the master device.