发明名称 |
COUNTER CIRCUIT |
摘要 |
A counter circuit includes a first Johnson counter circuit and a second Johnson counter circuit coupled in cascade. Each Johnson counter circuit includes a clock input, a data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input. The clock input of the first Johnson counter circuit is configured to receive an input clock signal. The clock input of the second Johnson counter circuit is connected to the second clock data output of the first Johnson counter circuit. A ripple counter circuit has a clock input and additional clock data outputs. The clock input of the ripple counter circuit is connected to the second clock data output of the preceding Johnson counter circuit. |
申请公布号 |
US2017111049(A1) |
申请公布日期 |
2017.04.20 |
申请号 |
US201514882868 |
申请日期 |
2015.10.14 |
申请人 |
STMicroelectronics (Grenoble 2) SAS |
发明人 |
Tubert Cedric |
分类号 |
H03K23/54 |
主分类号 |
H03K23/54 |
代理机构 |
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代理人 |
|
主权项 |
1. A counter circuit, comprising:
a first Johnson counter circuit having a first clock input and a first plurality of clock data outputs; a second Johnson counter circuit having a second clock input and a second plurality of clock data outputs; wherein the first clock input is configured to receive an input clock signal; and wherein the second clock input is connected to one of the first plurality of clock data outputs. |
地址 |
Grenoble FR |