INTER-POLY CONNECTION FOR PARASITIC CAPACITOR AND DIE SIZE IMPROVEMENT

摘要

The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.

主权项

1. A micro-electromechanical system (MEMS) package, comprising:
a CMOS substrate having one or more semiconductor devices arranged within a semiconductor body; a MEMS substrate having an ambulatory element, wherein the MEMS substrate is connected to the CMOS substrate by a conductive bonding structure arranged on a front-side of the MEMS substrate at a location that is laterally offset from the ambulatory element; and one or more conductive polysilicon vias extending through the MEMS substrate to the conductive bonding structure, wherein the one or more conductive polysilicon vias extend from a lower surface of the MEMS substrate that faces the CMOS substrate to a top surface of the MEMs substrate that faces away from the CMOS substrate, and wherein the one or more conductive polysilicon vias protrude outward from the top surface.