Hybrid polymoprhic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments

摘要

Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.

主权项

1. A computer program product for managing branch instructions in an emulation environment that is executing a program, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
populating a plurality of slots in a Polymorphic Inline Cache, each of the slots comprising a target address of a branch instruction of the program and a memory address of a compiled instruction representing the branch instruction;populating a plurality of entries in a branch target buffer residing within an emulated environment in which the program is executing, each of entries comprising an instruction address and a target address of a branch instruction of the program; andbased on an indirect branch instruction associated with the program being encountered:identifying, from the indirect branch instruction, a target address associated with the indirect branch instruction;comparing, by a processor, at least one address in each of the slots of the Polymorphic Inline Cache to the target address associated with the indirect branch instruction; andbased on none of the addresses in the slots of the Polymorphic Inline Cache matching the target address associated with the indirect branch instruction, searching in the branch target buffer to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.